Logarithmic Temperature Compensation For Detectors

ABSTRACT

The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T 0 . The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

This application is a divisional of U.S. patent application Ser. No. 11/621,454 filed Jan. 9, 2007 entitled LOGARITHMIC TEMPERATURE COMPENSATION FOR DETECTORS, which is a divisional of U.S. patent application Ser. No. 11/020,897 filed Dec. 22, 2004 entitled LOGARITHMIC TEMPERATURE COMPENSATION FOR DETECTORS, which are incorporated by reference.

BACKGROUND

A logarithmic amplifier (“log amp”) generates an output signal V_(OUT) that is related to its input signal V_(IN) by the following transfer function: V _(OUT) =V _(Y) log(V _(IN) /V _(Z))  Eq. 1 where V_(Y) is the slope and V_(Z) is the intercept. To provide accurate operation, V_(Y) and V_(Z) should be stable over the entire operating temperature range of the log amp. In a monolithic implementation of a progressive compression type log amp, temperature compensation of the slope V_(Y) is typically provided in the gain and detector cells since those are the structures that detennine the slope. Temperature stabilization of the intercept V_(Z), however, is typically provided at the front or back end of the log amp. For example, a passive attenuator with a loss that is proportional to absolute temperature (PTAT) may be interposed between the signal source and the log amp. Such an arrangement is disclosed in U.S. Pat. No. 4,990,803.

Another technique for temperature compensating the intercept of a log amp involves adding a carefully generated compensation signal to the output so as to cancel the inherent temperature dependency of the intercept. The intercept V_(Z) of a typical progressive compression log amp is PTAT and can be expressed as a function of temperature T as follows: $\begin{matrix} {V_{Z} = {V_{Z0}\left( \frac{T}{T_{0}} \right)}} & {{Eq}.\quad 2} \end{matrix}$ where T₀ is a reference temperature (usually 300° K) and V_(Z0) is the value of V_(Z) at T₀. Substituting Eq. 2 into Eq. 1 provides the following expression: $\begin{matrix} {V_{OUT} = {V_{Y}\quad{\log\quad\left\lbrack {\left( \frac{V_{IN}}{V_{Z0}} \right)\left( \frac{T_{0}}{T} \right)} \right\rbrack}}} & {{Eq}.\quad 3} \end{matrix}$ which can be rearranged as follows: $\begin{matrix} {V_{OUT} = {{V_{Y}\quad\log\quad\left( \frac{V_{IN}}{V_{Z0}} \right)} - \underset{\underset{{Temperature}\text{-}{dependent}}{︸}}{V_{Y}\log\quad\left( \frac{T}{T_{0}} \right)}}} & {{Eq}.\quad 4} \end{matrix}$ It has been shown that accurate intercept stabilization can be achieved by adding a correction signal equal to the second, temperature-dependent term in Eq. 4 to the output of a log amp, thereby canceling the temperature dependency. See, e.g., U.S. Pat. No. 4,990,803; and Barrie Gilbert, Monolithic Logarithmic Amplifiers, Aug. 1994, § 5.2.4. A prior art circuit for introducing such a correction signal is described with reference to FIG. 19 in U.S. Pat. No. 4,990,803.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an embodiment of a system for temperature compensating the intercept of a log amp according to the inventive principles of this patent disclosure.

FIG. 2 illustrates an embodiment of a temperature compensation circuit for a log amp according to the inventive principles of this patent disclosure.

FIG. 3 illustrates another embodiment of a temperature compensation circuit for a log amp according to the inventive principles of this patent disclosure.

FIG. 4 illustrates an embodiment of a technique for providing adjustable intercept compensation to a log amp according to the inventive principles of this patent disclosure.

FIG. 5 illustrates another embodiment of a technique for providing adjustable intercept compensation to a log amp according to the inventive principles of this patent disclosure.

DETAILED DESCRIPTION

FIG. 1 illustrates an embodiment of a system for temperature compensating the intercept of a log amp according to the inventive principles of this patent disclosure. The embodiment of FIG. 1 includes a temperature compensation circuit 12 that generates a correction signal SFIX having the form Y log (T/T₀) where Y is a generic slope factor. Since the expression T/T₀ will be used frequently, it will be abbreviated as H=T/T₀ for convenience. The correction signal S_(FIX) is applied to log amp 10 so as to temperature stabilize the intercept.

The temperature compensation circuit 12 generates the correction signal S_(FIX) by multiplying a signal having the form H log H by some other factor having a 1/H component. Thus, the H and 1/H cancel, and the only temperature variation in the correction signal is of the form log H. Any suitable scaling my also be applied to obtain the slope factor Y required for the particular log amp being corrected.

FIG. 2 illustrates an embodiment of a temperature compensation circuit according to the inventive principles of this patent disclosure. The embodiment of FIG. 2, which illustrates one possible technique for implementing the 1/H multiplication shown in FIG. 1, utilizes a transconductance (gm) cell 14. The transfer function of a generic gm cell has a hyperbolic tangent (tanh) form which may be stated a follows: $\begin{matrix} {I_{OUT} = {I_{T}\quad\tanh\quad\left( \frac{V_{i}}{V_{T}} \right)}} & {{Eq}.\quad 5} \end{matrix}$ where I_(T) is the bias or “tail” current through the gm cell, V_(i) is the differential input voltage, and V_(T) is the thermal voltage which may also be expressed as V_(T)=V_(T0)(T/T₀)=V_(T0)H. If the input signal to the gm cell is kept relatively small, the tanh function may be approximated as simply the operand itself: $\begin{matrix} {I_{OUT} \approx {I_{T}\frac{V_{i}}{V_{T}}}} & {{Eq}.\quad 6} \end{matrix}$

Now, to implement the generic gm cell in the compensation circuit of FIG. 2, H log H is used as the input V_(i) to the gm cell, the output current I_(OUT) is used as the correction signal in the fonn of a current I_(FIX), and V_(T0)H is substituted for V_(T): $\begin{matrix} {I_{FIX} \approx {I_{T}\frac{H\quad\log\quad H}{V_{T0}H}}} & {{Eq}.\quad 7} \end{matrix}$ Thus, H and 1/H cancel. If a temperature stable signal (sometimes referred to as a ZTAT signal where the Z stands for zero temperature coefficients) is used for I_(T), then I_(T)/V_(T0) is a temperature-stable constant that may be set to any suitable value Y to provide the correct slope. The final form of I_(FIX) is then given by: I_(FIX)≈Y log H  Eq. 8 Therefore, the use of a transconductance cell with its inherent 1/H factor provides a simple and effective solution to generating a correction signal having the requisite log H characteristic.

FIG. 3 illustrates another embodiment of a temperature compensation circuit according to the inventive principles of this patent disclosure. The embodimient of FIG. 3 uses a pair of diode-connected transistors biased by ZTAT and PTAT currents to generate the H log H function, which is then applied to a gm cell in a tightly integrated translinear loop.

Diode-connected transistors Q3 and Q4 are referenced to a positive power supply V_(POS), and are biased by currents I_(P) and I_(Z), respectively. I_(Z) is ZTAT, while I_(P) is a PTAT current. The base-emitter voltages of Q3 and Q4 are: $\begin{matrix} {V_{{BE}3} = {V_{\quad T}\ln\quad\left( \frac{\quad I_{\quad P}}{\quad I_{\quad S}} \right)}} & {{Eq}.\quad 9} \\ {V_{{BE}4} = {V_{T}\ln\quad\left( \frac{I_{Z}}{I_{S}} \right)}} & {{Eq}.\quad 10} \end{matrix}$ and therefore, the ΔV_(BE) across the bases of Q3 and Q4 is: $\begin{matrix} {{{\Delta\quad V_{BE}} = {{V_{{BE}3} - V_{{BE}4}} = {{V_{T}\ln\quad\left( \frac{I_{P}}{I_{S}} \right)} - {V_{T}\ln\quad\left( \frac{I_{z}}{I_{S}} \right)}}}}{{\Delta\quad V_{BE}} = {V_{T}\ln\quad\left( \frac{I_{P}}{I_{Z}} \right)}}} & {{Eq}.\quad 11} \end{matrix}$ Since I_(P) can be expressed as I_(P)=I_(Z)H, and V_(T)=V_(T0)H: $\begin{matrix} {{{\Delta\quad V_{BE}} = {V_{T0}H\quad\ln\quad\left( \frac{I_{Z}H}{I_{Z}} \right)}}{{\Delta\quad V_{BE}} = {V_{T0}H\quad\ln\quad H}}} & {{Eq}.\quad 12} \end{matrix}$ Thus, the ΔV_(BE) of Q3 and Q4 provide a signal having the fonn H log H, which is then applied as the input signal V_(i) to the gm cell.

The gm cell is implemented as a differential pair of emitter-coupled transistors Q1 and Q2 that are biased by a ZTAT tail current I_(T). The base-emitter junctions of Q1 and Q2 complete the translinear loop with the base-emitter junctions of Q3 and Q4. The output signal I_(OUT) from the differential pair is taken as the difference between the collector currents I₁ and 1 ₂ of transistors Q1 and Q2, respectively. Substituting ΔV_(BE) of Eq. 12 as V_(i) in Eq. 6 provides: $\begin{matrix} {{I_{OUT} \approx {I_{T}\frac{V_{T0}H\quad\ln\quad H}{V_{T0}H}}}{I_{OUT} \approx {I_{T}\ln\quad H}}} & {{Eq}.\quad 13} \end{matrix}$ By exercising some care in the selection of the scale factor for I_(T), the proper slope factor Y may be obtained. Since the output signal I_(OUT) is in a differential form, it is easy to apply it as the compensation signal I_(FIX) to the output of any log amp having differential current outputs. This is especially true in the case many progressive compression log amps. I_(FIX) can simply be connected to the same summing nodes that are used to collect the current outputs from the detector cells for the cascaded gain stages.

FIG. 4 illustrates an embodiment of a technique lor providing adjustable intercept compensation to a log amp according to the inventive principles of this patent disclosure. In some implementations, the compensation techniques described above may be frequency dependent. That is, although adding a compensation signal of the form Y log H may stabilize the intercept over the entire operating temperature range at a given frequency, a different amount of compensation may be required at different operating frequencies. The embodiment of FIG. 4 provides a terminal 16 that allows a user to vary the amount of compensation depending on the operating frequency.

The example embodiment of FIG. 4 is fabricated on an integrated circuit (IC) chip, preferably including the target log amp to be temperature compensated. A transconductance cell 14, which generates the Y log H correction signal, is biased by a tail current I_(T). The tail current is generated by a transistor Q_(T). which in turn is biased by a voltage V_(BIAS). The magnitude of the tail current is determined by the combination of an internal resistor R_(INT) which is fabricated on the chip, and an external resistor R_(EXT), which may be connected through terminal 16. The appropriate value of R_(EXT) may be provided to the user through a lookup table, equation, etc.

FIG. 5 illustrates another embodiment of a technique for providing adjustable intercept compensation to a log amp according to the inventive principles of this patent disclosure. As in the embodiment of FIG. 4, the embodiment of FIG. 5 includes a transconductance cell 14 biased by a tail current I_(T) generated by transistor Q_(T). Rather than setting the tail current directly through an external resistor, however, the current through Q_(T) is set by an internal resistor R_(INT) in combination with an operational amplifier (op amp) 18 arranged to drive the base of Q_(T) in response to an adjustment signal V_(ADJ) which is applied externally by the user through terminal 16. This eliminates any potential problems with mismatches between internal and external resistors. As an added feature, an on-chip reference voltage V_(REF), which is typically available internally on the IC, can be made available to the user through another terminal 20. This enables the user to set the adjustment signal V_(ADJ) using external divider resistors R1 and R2.

This patent disclosure encompasses numerous inventions relating to temperature compensation of log amps. These inventive principles have independent utility and are independently patentable. In some cases, additional benefits are realized when some of the principles are utilized in various combinations with one another, thus giving rise to yet more patentable inventions. These principles can be realized in countless different embodiments. Only the preferred embodiments have been described. Although some specific details are shown for purposes of illustrating the preferred embodiments, other equally effective arrangements can be devised in accordance with the inventive principles of this patent disclosure.

For example, some transistors have been illustrated as bipolar junction transistors (BJTs), but CMOS and other types of devices may be used as well. Likewise, some signals and mathematical values have been illustrated as voltages or currents, but the inventive principles of this patent disclosure are not limited to these particular signal modes. Also, the inventive principles relating to user-adjustable compensation are not limited to a specific form of temperature compensation, or even to temperature compensation in general. An integrated circuit according to the inventive principles of this patent disclosure may have a user-accessible terminal to adjust the magnitude of any type of compensation, e.g., temperature or frequency, to any type of measurement device.

The embodiments described above can be modified in arrangement and detail without departing from the inventive concepts. Thus, such changes and modifications are considered to fall within the scope of the following claims. 

1. A temperature compensation circuit comprising: a first junction biased by a first bias current; a second junction biased by a second bias current, where the first and second diodes are arranged to generate a first signal having a logarithmic temperature dependency; and a multiplier to generate a compensation signal by multiplying the first signal by a third bias signal.
 2. The temperature compensation circuit of claim 1 where the first and second junctions comprise diode-connected transistors arranged to generate the first signal as a ΔV_(BE) signal.
 3. The temperature compensation circuit of claim 2 where the multiplier comprises a differential pair of transistors arranged to form a translinear loop with the first and second junctions.
 4. The temperature compensation circuit of claim 3 where the differential pair of transistors is biased by the third bias signal.
 5. The temperature compensation circuit of claim 4 further comprising a terminal, to enable a user to adjust the magnitude of the third bias signal.
 6. The temperature compensation circuit of claim 5 where the third bias signal comprises a ZTAT current.
 7. The temperature compensation circuit of claim 2 where: the first current comprises a ZTAT current; and the second current comprises a ZTAT current.
 8. A system comprising: a temperature compensation circuit to generate a correction signal by multiplying a signal having a logarithmic temperature dependency and a factor H by another signal having a 1/H component, thereby cancelling the factor H, where H is a function of temperature. 